General electric alternating current (AC) power (“mains power” or “mains electricity” or simply “mains”) may need to be converted into direct current (DC) power for use by various electronic consumer devices. A power management system can convert AC power from a main power source into DC power using components that experience low losses in power dissipation, such as, for example, inductors, diodes, capacitors, transformers and other switches (e.g., junction gate field-effect transistors, metal-oxide-semiconductor field-effect transistors, etc.). Losses in the main source may be decreased by focusing on the harmonics of the current drawn from the main source and the phase relationship between the mains voltage and the current drawn from the main source. The efficiency of the mains power source can be measured by a power factor. The power factor of an AC to DC electric power system can be defined as the ratio of the real power drawn from the main source compared to the product of the root means square (rms) voltage Vrms and the rms current Irms.
A power factor corrector (PFC), which may include a bridge rectifier, a switch-mode power supply (SMPS), and control circuits, can be used to help maximize the power factor in power management systems and can also be used for power management in personal computers, adapters, lighting, and so on. The power factor can therefore be a significant parameter in evaluating a PFC's overall performance.
A PFC circuit can be used in applications such as power converters to control the phase of the input current and help maximize power in power management systems. A PFC circuit, which can also referred to simply as a “PFC”, may be needed for an SMPS having power levels above, for example, 75 watts. For a power level above approximately 300 watts, a CCM (Continuous-Conduction Mode) operation becomes attractive because this can allow for the use of small EMI (Electromagnetic Interference) filters.
Some PFC circuits can use fixed frequency in CCM applications. Close to the main zero-crossing, CCM cannot be maintained, and a changeover from a BCM (Boundary Conduction Mode) to a DCM (Discontinuous Conduction Mode) may occur in association with a rising frequency. Unfortunately, this feature can result in a lower efficiency close to the main zero-crossing.
For optimum efficiency, it may be advantageous to use CCM at higher power levels around the peak voltage of the main power supply and then use DCM in other situations.
Some DCM applications may employ a topology involving Ton (Timer On) control for the PFC switch. Ton control can offer the advantage for BCM of automatically correcting the mains current shape for a high power factor. This is because di/dt=Vmains/Lind, wherein Lind is the main inductor value and Vmains represents the mains voltage. Thus, with a fixed Ton, the primary peak current can be proportional to the momentary mains voltage. For CCM, the primary current can depend on the current at the end of the previous switching cycle and the switch conduction interval Ton. Therefore, on time control in the manner used in DCM cannot be employed in CCM operations.
Some CCM operational techniques use a method referred to as “average current control”. This approach can be based on the fact that the duty cycle of the secondary stroke equals Vin/Vout where Vin represents the input voltage of the PFC and Vout represents the output voltage. FIG. 1 depicts a waveform diagram 100 illustrating the concept of average current control CCM. The waveforms shown in FIG. 1 demonstrate that when the duty cycle becomes smaller than the equilibrium value, the duration of the secondary stroke may also become smaller. This situation offers less reduction for the inductor current and therefore can result in an increase in the current as compared to the current at the start of the switching cycle (e.g., see curve 102 in FIG. 1).
When the duty cycle is higher than the equilibrium, an increase in the reduction of the inductor current can occur, and therefore a decrease in the current can also occur as compared to the current at the start of the switching cycle (e.g., see curve 106 in FIG. 1). A signal indicative of the duty signal can be generated by a ramp signal 108 (ramp for PWM (Pulse Width Modulation)) and a control signal 110. The ramp signal 108 and control signal 110 can be subject to a comparison operation by a comparator, which can generate the signal indicative of the duty cycle. This means that equilibrium can occur when the control signal 110 is proportional to Vin/Vout. As the output voltage ‘Vout’ may be normally regulated to a fixed value, the result can be that the control signal may be proportional to Vin. By making the control signal 110 proportional to the sensed current, the system can generate an input current proportional to the momentary mains voltage, which can fulfill the power factor requirement.
FIG. 2 depicts a schematic diagram of a PFC circuit 130 that applies the average current control principle. The circuit 130 shown in FIG. 2 can include a pair of diodes 132, 124 and another pair of diodes 136, 138. The diodes 134 and 138 can connect to ground 140. An inductor 144 can connect to diodes 132 and 138, and can also connect to ground 140.
The circuit 130 can further include an oscillator 146 that can connect to the negative input of an amplifier 148 that provides PWM waveforms that can be supplied to a transistor 150. The inductor 144 can also connect to the transistor 140 and a diode 152. An output capacitor 154 can connect to the output of the diode 152 and ground 141. The output capacitor 154 can be located between a ground output (“Out Gnd”) and the output of the diode 152.
The circuit 130 can further include a resistor 158 (“Rop”) that can be coupled to a shunt resistor 156 (“Rshunt”), ground 140 and the diodes 138 and 134. The shunt resistor 156 can be further connected to a resistor 160, which in turn can be coupled to a capacitor 164 and a current amplifier 162. The capacitor 164 can be further coupled to a capacitor 166 and a resistor 168, which can also be tied to the output of the current amplifier 162. The capacitor 166 and the resistor 168 can be connected in parallel with one another and can further connect to the positive input of the amplifier 148 along with the output of the current amplifier 162. That is, the current amplifier output (“Vca”) can connect to the positive input of the amplifier 148.
FIG. 3 depicts a schematic diagram of a control circuit 180 that utilizes a multiplier approach. The circuit 180 generally includes an AC voltage source 182 that can be offset by a diode 184. The AC voltage source 182 can supply a voltage VAC to a resistor 186 (“RIAC”) and an inductor 212. The resistor 186 can be coupled to a multiplier 188 that in turn can connect to a resistor 190 and the positive input of an amplifier 192 whose output can connect to a latch 194. The latch 194 in turn can be coupled to a gate driver logic component 200 that in turn can connect to a transistor 219.
A resistor 198 can further connect to the transistor 214 and ground 196. The transistor 214 can be further coupled to the inductor 212 and a diode 216. A capacitor 218 can connect to the diode 216 and to the resistor 198 (and also to ground 196). The capacitor 218 can also be implemented in parallel with a load 220. A resistor 210 can connect to the capacitor 218 and the diode 216 and also to a resistor 208 and the negative input of an error amplifier 202 that can output a voltage VEA. The resistor 208 can also be coupled to ground 206. A reference voltage 204 (“VREF”) can connect to the positive input of the error amplifier 202. The output from the error amplifier 202 in turn can be coupled to the multiplier 188.
In the configuration of circuit 180, the control voltage VEA that can be output from the error amplifier 202 can set the desired power level so that the PFC output voltage may be equal to the desired level while delivering power to the load 220. The multiplier 188 can then multiply the control output signal with the mains voltage shape so as to provide a desired current level, which can be then compared with a sensed current level and used to reset the latch 194 in order to define a primary current peak level. The switching cycle can be started by a Zcd (zero current detection) signal in order maintain the system in a BCM.
For a system in BCM operation, the input current as drawn from the mains can be proportional to the primary peak current and also proportional to the “on time” of the PFC switch. This makes it easy to render a satisfactory power factor. When the system goes to DCM, the average current may be lower for the same primary peak current, because of the ringing interval that arises after the end of the secondary stroke where no current may be drawn from the mains. Some configurations may use a PFC where this effect can be compensated by an additional adaption of the primary peak current based on a ratio: Tper/(Ton+Tsec).
FIG. 4 depicts a group of equations 230 that can define factors for a PFC circuit. Providing for a high power factor means that the input current drawn by the PFC may be proportional to the momentary mains voltage. Ideally, this can be represented by defining a factor k2 according to the equations 230 shown in FIG. 4. That is:Iin=k2·VmainsPin=Vmains·IinPin=Vmains·(k2·Vmains)Pin=Vmains2·k2
Thus, the momentary input current may equal the momentary mains voltage times a factor k2. This means that the momentary input power may be proportional to the square of the momentary input voltage.
FIG. 5 depicts a graph 240 and a graph 250, which demonstrate the relationship between momentary current voltage and power for a PFC circuit according to the equations 230 shown in FIG. 4. Graph 240 and curve 242 plot data indicative of Vmains(t) with respect to time t based on the equation Pin (t,K2):=Vmains(t)2·k2 wherein k2b:=0.002. Graph 250 depicts a curve 252 and a curve 254 respectively for Pin(t,k2b) and Pin(T,k2Aa) wherein k2a=1×10−3 and k2b=2×10−3.
FIG. 6 depicts a graph 260 depicting average power over a mains half cycle for a PFC circuit. A curve 262 and a curve 264 in graph 260 demonstrate that for the average power over a mains half cycle, the average value of the power is half of the peak value of the square of a sine wave:
      Pin_av    ⁢          (                        k          ⁢                                          ⁢          2                ,        Vmainspeak            )        =                              Vmainspeak          2                2            ·      k        ⁢                  ⁢    2  
Thus, fixing k2 may mean that the power level can be proportional to the square of the mains voltage amplitude. Accordingly, the gain of the closed loop can be proportional to the square of the mains voltage amplitude. In some cases, it may be desirable to have a fixed gain of the total control loop. A constant gain may prevent a 0 db loop gain frequency for closed loop shifts. In this manner, an optimum dynamic response may be possible for universal mains voltage while maintaining optimum stability for the loop.
K2 therefore can include a mains voltage that may be compensated by 1/Vmains{circumflex over ( )}2, which can allow the gain from the control to output power to be compensated for the mains voltage amplitude.
In a practical PFC application, it may not be easy to define behavior according to this desired factor K2. DCM controllers, for example, can may on time control with BCM or fixed frequency DCM. In BCM, the factor K2 may be more or less defined as a fixed on time, which can cause a peak current, ‘Ipeak’, to be proportional to the momentary mains voltage, and thus in BCM, the input current may be proportional to ‘Ipeak/2’, which may also be proportional to the mains voltage. In DCM with fixed frequency, the average current may be no longer ‘Ipeak/2’ because of the changing ratio between the primary+secondary stroke and a period of time.
With conventional techniques and circuits such as discussed above, it may be possible to configure a CCM PFC circuit or a DCM PFC circuit. To date, DCM and CCM have not been combined in a manner that allows a PFC circuit to operate for DCM and CCM within a main half cycle. In addition, the loop gain and dynamic behavior are different in CCM and DCM in PFC circuits, which can make it more complex to define the closed loop and obtain a dynamic performance. Another problem with PFC circuits relates to potential instabilities (e.g., short long cycles) that can occur in CCM for a duty cycle greater than 50%. In addition, the operating frequency in BCM can lead to large frequencies during part of the mains half cycle.
Accordingly, there is a long-felt need for AC/DC power converters employed in power management systems to address the foregoing problems.